1. Field of the Invention
The present invention relates to an information processing apparatus, in particular, to an information processing apparatus in which data access is performed using a register bank method (see Japanese Laid-Open Patent Application No. 4-14147).
2. Description of the Related Art
An information processing apparatus in which data access is performed using the register bank method is, as shown in FIG. 1, provided with a CPU (Central Processing Unit) body 1 and a register-bank memory 2 having a single port. The CPU body 1 and register-bank memory 2 are connected with each other via a special internal address bus, internal data bus 4 and control-signal line 5, other than the data bus and address bus used for connecting with peripheral apparatuses.
The CPU body 1 includes:
a general-use register set (register array) 6 which is made of a plurality of registers; PA1 a special register (CBNR) 7 which specifies bank numbers of the register-bank memory 2; PA1 a bank address buffer 8 which integrates signals, which indicate currently used bank numbers of banks in a memory unit 13 of the register-bank memory 2 and are obtained from the special register 7, with register selection control signals RGS0 through RGSn which indicates register numbers of registers in the banks (ordinarily, a plurality of registers being included in a bank), and thus supplies signals RA0 through RAm to the register-bank memory 2; PA1 an address circuit 9 to which the current bank numbers and RGS0 through RGSn are input; PA1 a decoding circuit 10 to which these signals are input from the address circuit 9; PA1 a command control unit 11 which supplies signals including RBCK (control clock signal), RBCE (memory enable signal), RBWEB (read/write control signal) to the register-bank memory 2; and PA1 an input/output circuit 12 which sends to and receives from the register-bank memory 2 RB0 through RBn (register data). PA1 a memory unit 13; PA1 an address circuit 14 which receives the above-mentioned RA0 through RAm; PA1 a decoding circuit 15 which receives the forward and inverse outputs from the address circuit 14; PA1 a general-use register set comprising a plurality of registers in a central processing unit body; and PA1 a register-bank memory having memory regions corresponding to said plurality of registers and connected to said central processing unit; PA1 and wherein an output signal of an address circuit included in said central processing unit is supplied to said register-bank memory. PA1 a general-use register set comprising a plurality of registers in a central processing unit body; and PA1 a register-bank memory having memory regions corresponding to the plurality of registers and connected to the central processing unit; PA1 and wherein an output signal of a decoding circuit included in the central processing unit is supplied to the register-bank memory. PA1 the register-bank memory is divided into a plurality of modules; and PA1 the information processing apparatus further comprises module selecting means which deactivates a module of the plurality of modules, the module to be deactivated being one which is not currently accessed.
The address circuit 9 has, as shown in FIG. 2, circuits including inverters for the RGS0 through RGSn, receives the RGS0 through RGSn, and supplies forward and inverse signals thereof (IA0 through IAn and IA0B through IAnB in FIG. 2). Further, the decoding circuit 10 is, as shown in FIG. 3, made of four-input NAND circuits and inverters, receives output (IA0 through IA3 and IA0B through IA3B in FIG. 3), and supplies decoded signals (RG0 through RG15 in FIG. 3).
The register-bank memory 2 includes:
a control circuit 16 which receives the above-mentioned signals including RBCK, RBCE and RBWEB and controls the address circuit 14; and
an input/output circuit 17 which sends to and receives from the register-bank memory 2 the above-mentioned RB0 through RBn.
The above-mentioned address circuit 14 includes, as shown in FIG. 4, circuits made of a NAND circuit and an inverter, receives from the above-mentioned bank address buffer 8 the RA0 through RAm and supplies the forward and inverse signals thereof (IA0 through IAm and IA0B through IAmB in the figure). Input signals RA0 through RAm relevant to the above-mentioned RGS0 through RGSn in the CPU body 1, and RAn+1 through RAm correspond to the current bank numbers starting from CBNR 7 in the CPU body 1. Further, a signal ICE shown in FIG. 4 is supplied by the control circuit 16 and controls driving of the address circuit 14.
The decoding circuit 15 includes, as shown in FIG. 5, five-input NAND circuits receiving signals from the address circuit 14 and NOR circuits, and receives outputs (IA0B through IA4B and IA0 through IA4 in the figure) from the address circuit 14, and outputs decoded signals (WL0 through WL31 in the figure).
The memory unit 13 includes, as shown in FIG. 6, a memory-cell array unit 13a and a precharging unit 13b, and is provided with a memory space corresponding to a memory space of the general-use register set 6. Further, the memory unit 13 sends to and receives from the decoding circuit the decoded signals (WL0 through WLn-1 in the figure), and sends to and receives from the input/output circuit 17 the signals (BL0 through BLm-1, BLB0 through BLBm-1 in the figure). A signal ICKB shown in the figure is supplied by the control circuit 16 and controls the precharging.
The input/output circuit 17 includes, as shown in FIG. 7, a writing circuit 17a. The input/output circuit 17 sends to and receives from the memory unit 13 the signals (BL0 through BLm-1, BLB0 through BLBm-1), and also sends to and receives from the input/output circuit 12 in the CPU body 1 data (RB0 through RBn). A signal IWE shown in the figure is supplied by the control circuit 16 and controls reading/writing.
The control circuit 16 includes, as shown in FIG. 8, NAND circuits and inverters and receives from the command control unit 11 in the CPU body 1 the signals RBCK, RBCE and RBWEB, and outputs the control signals ICE, ICKB and IWE.
FIG. 9 shows the timing of reading/writing and precharging of the precharging unit 13b in the memory unit 13. When the signal RBCK from the CPU body 1 is at a low level, the signal ICKB is at a high level and all of the memory cells (MC) are thus precharged. When the ICKB is in the high level, none of the signals WL0 through WLn-1 are selected (see FIG. 5). Further, when the signal RBCK is at the high level, according to a current address, one of the signals WL0 through WLn-1 is selected. When, in this state, the signal RBWEB is at the low level, the signal IWE is at the high level and a writing operation is performed on the memory cells. When, in the same state, the signal RBWEB is at the high level, the IWE signal is at the low level and a reading operation is performed on the memory cells. The signal RBCE is maintained to be at the high level during a register accessing operation.
The above-described information processing apparatus in the related art using the register bank method operates as described below.
When the CPU body 1 executes a command and reads data from the registers, data in the general-use register set 6 is read out. At this time, the register-bank memory 2 has the signals RA0 through RAm supplied thereto from the bank address buffer 8 and thus enters a read state. However, the CPU body 1 gives a higher priority to and therefore receives data read from the general-use register set 6, not data read from the register-bank memory 2.
When the CPU body 1 executes a command and writes data to registers, data is written in the general-use register set 6, and simultaneously the same data is written in a memory region, corresponding to a bank number currently being used, of the general-use register set 6, in the register-bank memory 2. For example, when the command to be executed is an adding command (a result of (R2+R15) is stored as R15, that is, `add: g. 1 r2, r15` in a programming language), after a calculation of (R2+R15) is performed, the result is written in a register R15 of the general-use register set 6 and simultaneously the same result is written in a region for the register R15 in the register-bank memory 2.
Thus, the register-bank memory 2 has data the same as that which the general-use register set 6 has, in relevant regions thereof.
A case where the information processing apparatus did not use the above-described register bank method will now be considered. In such a case, data currently being stored in the general-use register set 6 and being currently used may be switched to other new data stored in a new bank of externally provided memory. Such an operation may be referred to as register bank switching. When the register bank switching is performed, the data, which is the same as that currently being stored in the general-use register set 6, is written in another bank of externally provided memory. Thus, the data currently being used is saved. Thereby, the other new data stored in the other new bank of externally provided memory can be loaded in the general-use register set 6 and thus the data in the general-use register set can be updated.
In contrast to this, when the register bank method is used, the register-bank memory regularly has data, stored therein, the same as that of the general-use register set 6. As a result, it is not necessary to specially perform the above-mentioned operation of writing the data the same as that currently being stored in the general-use register set 6 so as to save the data. Only the operation of loading the new data in the general-use register set 6 can achieve such bank switching.
However, in the information processing apparatus in which data accessing is performed using the register bank method in the related art, it is necessary to provide in the register-bank memory 2 the address circuit 14 and decoding circuit 15 similar to the address circuit 9 and decoding circuit 10 in the CPU body 1. In order to supply power to the address circuit 14 and decoding circuit 15, required power consumption increases in the register-bank memory 2.
In order to prevent the required power consumption from increasing, a method of dividing a bit line or a word line is known (see Japanese Patent Publication No. 3-4995, Japanese Patent Publication No. 3-11035 and Japanese Patent Publication No. 3-77399). However, in these publications, chip area requirement increases in comparison to a case where a bit line or a word line is divided.